Users of digital to analog converters generally wish to see high conversion accuracy and high conversion rates.
Flash converters and pipeline converters are known to provide high conversion speeds. Flash converters convert an input word in a single go and exhibit only a relatively small conversion delay whereas pipeline converters segment the conversion process into multiple steps and hence can achieve high throughput, at the expense of a pipeline delay and increased complexity.
A particularly popular analog to digital converter type is the successive approximation converter. This converter represents a good compromise between cost and speed and can be made to be very accurate. A successive approximation converter performs successive bit trials to see, whether, once the bit being trialed is set if the analog value that it is seeking to convert is greater than or less than the equivalent value represented by the bit being trialed, in conjunction with the sum of any previously kept bits. Thus the successive approximation converter seeking to produce an eight bit output result performs eight bit trials (or more if the converter included redundancy).
U.S. Pat. No. 6,239,734 discloses an analog to digital converter having three converters which co-operate such that each bit trial can determine two bits within the digital word. An example shown in FIG. 7 of U.S. Pat. No. 6,239,734 discloses the conversion of a six bit word. An analog input signal is presented which has a value, when converted, that corresponds to “110011”. In accordance with the normal successive approximation process a first register SAR is set to trial the word “100000”. Additionally a second register SAR+ is set to trial the word “110000” and a third register SAR− is set to trial the word “010000”. In this first trial the analog value is greater than each of the trial words in the SAR, SAR+ and SAR− registers and hence the first two bits of trial can be set to “11”. In a second trial the two bits being tested are set to “10, 11 and 01”, in the registers respectively such that the first register trials “111000”, the SAR+ register trials “111100” and the SAR− register trials “110100”. At the end of this second trial the analog value is less than each of the trial words hence the next two bits can be set to “00” thus four bits being determined in only two trial steps. In the third step the “10, 11 and 01” pattern is presented to each of the registers for bits five and six with the previous four bits being set to “1100” as determined by the first two trial steps. In the final steps two of the trial words are less than the analog value and the third trial word is not, thereby recovering the converted word of “110011” with the end bit word being converted in
      n    2    ⁢          ⁢      trials    .  
Thus a potential doubling of conversion speed has been achieved. However this is at the cots of having to fabricate three analog to digital conversion engines.